3822_03 Datasheet, PDF (215/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.6 A-D converter
(3) CPU mode register (address 003B16)
The CPU mode register consists of the stack page selection bit and control bits for the internal system
clock φ. Use the A-D converter in the state where bits 5 and 7 of this register are “0” (high-speed mode
or middle-speed mode).
Figure 2.6.6 shows the structure of the CPU mode register.
The operating clock of the A-D converter is the main clock input frequency f(XIN)/2. Use the A-D
converter in the state of f(XIN) 500 kHz.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register (CPUM) [Address 3B 16]
B
Name
0 ^{Processor mode bits}
1
Functions
b1b0
00: Single-chip mode
01:
10: Not available
11:
2 ^{Stack page selection 0: 0 page}
bit
1: 1 page
3 Fix this bit to “1.”
At reset R W
0
0
0
1 11
4 Port XC switch bit
0: I/O port
0
1: XCIN, XCOUT
5 ^{Main clock (XIN–XOUT) 0: Oscillating}
0
stop bit
1: Stopped
6 Main clock division 0: f(XIN)/2
1
ratio selection bit
(high-speed mode)
1: f(XIN)/8
(middle-speed mode)
7
Internal system clock
selection bit
0: XIN–XOUT selected
(middle-/high-speed mode)
0
1: XCIN–XCOUT selected
(low-speed mode)
Fig. 2.6.6 Structure of CPU mode register
3822 GROUP USER’S MANUAL
2–149