3822_03 Datasheet, PDF (182/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O
‘At the time when a transmit shift operation
starts, the transmit shift register shift com-
pletion flag (bit 2) of the serial I/O status
register is cleared to “0.” ^V4
’After the lapse of a 1/2 period ^V5 of the shift
clock from a transmission start of stop bit,
the transmit shift register shift completion flag
is set to “1.” ^{V2 V4}
b0
D7 D6 D5 D4 D3 D2 D1 D0
Transmit shift register
Serial I/O status
register
[Address 1916]
Serial I/O status
register
[Address 1916]
ST
P45/TxD
1
0
b2
SP
P45/TxD
0
1
b2
V4: When an internal clock is used as a syn-
chronizing clock, supplying the shift clock
to the transmit shift register stops auto-
matically at the completion of 8-bit transmission. However, when the next transmit data is written
to the transmit buffer register while the transmit shift register shift completion flag is “0,” supplying
the shift clock is continued.
V5: In the case of 2 stop bits, after the lapse of a 1/2 period of the shift clock from a start of the
second stop bit transmission.
Shift clock
Write “1”
Transmit buffer
empty flag
Transmit shift
register shift
completion flag
Write transmit data to transmit buffer register
Write next transmit data
TXD
ST D0 D1 D2
D6 PAR SP SP ST D0
Fig. 2.5.11 Transmit timing example in UART mode
2–116
3822 GROUP USER’S MANUAL