3822_03 Datasheet, PDF (267/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.10 Oscillation circuit
sLow-speed mode
The clock obtained by dividing the frequency f(XCIN) input to the XCIN pin by 2 is an internal clock φ.
In the low-speed mode, the oscillation of the main clock is stopped by setting the main clock (XIN–
XOUT) stop bit to “1,” so that the low-power operation can be attained.
When changing to the middle- or high-speed modes:
Change the mode according to the following procedure.
Œ Set the main clock (XIN–XOUT) stop bit (bit 5) of the CPU mode register to “0.”
 Generate the oscillation stabilizing time of XIN input by software.
Ž Set the internal system clock selection bit (bit 7) of the CPU mode register to “0.”
 Specify the main clock division ratio selection bit (bit 6) of the CPU mode register.
Notes1: Make a mode change from the middle- or high-speed modes to the low-speed mode after the
oscillation of both the main clock and the sub-clock is stabilized (for oscillation stabilizing
time, ask the resonator manufacturer for information).
2: For the sub-clock, the stabilizing of oscillation requires much time. When making a change
from the middle- or high-speed modes to the stop mode and then making a return from the
stop mode while the sub-clock oscillates, the oscillation of the sub-clock is not yet stabilized
even when the main clock has become stable and the CPU has been restored.
3: For a mode change, set to f(XIN) > f(XCIN) ! 3.
(2) Oscillating operation in the stop mode
After the stop mode is provided by executing the STP instruction, every oscillation stops and the
internal clock φ stops at the “H” level. At the time when restoration is made from the stop mode by
rest input or by the occurrence of an interrupt request for restoration, oscillation starts.
For the details of the stop mode, refer to “2.8.1 Stop mode.”
(3) Oscillating operation in the wait mode
After the wait mode is provided by executing the WIT instruction, the internal clock φ supplied to the
CPU stops at the “H” level. As oscillation is continued, the supply of internal clock φ to the peripheral
units is continued.
At the time when restoration is made from the wait mode by reset input or by the occurrence of an
interrupt request for restoration, the supply of internal clock φ to the CPU starts. For the details of the
wait mode, refer to “2.8.2 Wait mode.”
3822 GROUP USER’S MANUAL
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