3822_03 Datasheet, PDF (184/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O
After the lapse of a 1/2 period of the shift
clock from a reception start of stop bit, the
receive buffer full flag (bit 1) of the serial
I/O status register is set to “1.” And a serial
I/O receive interrupt request occurs.
‘Error flag detection is performed concurrently
with the occurrence of a serial I/O receive
interrupt request.
V4: The receive buffer full flag is cleared to “0”
by reading out the receive buffer register.
Shift clock
RXD (SP)
Serial I/O status
register
[Address 1916]
Write “1”
Receive enable bit
RXD
Start receiving at falling of ST
Check that ST is “L” level
ST D0 D1 D2
D6 PAR _{SP SP}
Shift clock
0
1
b1
ST D0
Fig. 2.5.12 Receive timing example in UART mode
(3) Processing upon occurrence of errors
sParity error, framing error, or summing error
When a parity error, a framing error, or a summing error occurs, the flag corresponding to each error
in the serial I/O status register is set to “1.” These flags are not cleared to “0” automatically, so set
them to “0” by software.
These flags are set to “0” by one of the following operations.
•Set the receive enable bit to “0”
•Write data (arbitrary) into the serial I/O status register
sOverrun error
An overrun error occurs when data is already input in the receive buffer register and yet all data is
input in the receive shift register.
If an overrun error occurs, the data of the receive shift register is not transferred and the data of the
receive buffer register is held. At this time, even if the data of the receive buffer register is read out,
the data of the receive shift register is not transferred.
Consequently, the data of the receive shift register becomes unreadable, so that the receive data
becomes invalid.
If an overrun error occurs, after set the overrun error flag of the serial I/O status register to “0”,
perform a receive operation again.
The overrun error flag is set to “0” by one of the following operations.
•Set the serial I/O enable bit to “0”
•Set the receive enable bit to “0”
•Write data (arbitrary) into the serial I/O status register
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3822 GROUP USER’S MANUAL