3822_03 Datasheet, PDF (181/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O
sTransmit operation in the UART mode
Transmit operation in the UART mode is described below.
qStart of transmit operation
A transmit operation is started by writing transmit data into the transmit buffer register (address
001816) in the transmit enable state.^V1
qTransmit operation
ŒBy writing transmit data into the transmit buffer
register, the transmit buffer empty flag (bit 0)
of the serial I/O status register (address
001916) is cleared to “0.”
The transmit a data written in the transmit
buffer register is transferred to the transmit
shift register.^V2
ŽWhen a data transfer from the transmit buffer
register to the transmit shift register is com-
pleted, the transmit buffer empty flag is
set to “1.”^V3
The transmit data transferred to the transmit
shift register is output from the P45/TxD pin
in synchronization with the falling of the shift
clock, beginning with the start bit. A start bit,
a parity bit and a stop bit are automatically
generated and output in accordance with the
contents set in the UART control register.
Data bus
[Address 1816]
Write transmit data
Transmit buffer register
b0
Serial I/O status
1
register
[Address 1916]
0
Transmit buffer register
Transfer transmit data
Transmit shift register
Serial I/O status
0
register
[Address 1916]
1
b0
b0
D7 D6 D5 D4 D3 D2 D1 D0
Transmit shift register
ST
P45/TxD
The data is output from the least significant
bit of the transmit shift register. Each time 1-
bit data is output, the data of the transmit
shift register is shifted by 1 bit toward the
least significant bit.
b0
D7 D6 D5 D4 D3 D2 D1
Transmit shift register
D0
P45/TxD
V1: Initialization of register or others for a trans-
mit operation. Refer to “2.5.4 Register set-
ting example.”
V2: When the transmit interrupt source selection bit (bit 3) of the serial I/O control register (address
001A16) is set to “0,” a serial I/O transmit interrupt request occurs immediately after transfer in .
When this bit is set to “1,” a transmit interrupt request occurs at the time of ’.
V3: While the transmit buffer empty flag is “1,” it is possible to write the next transmit data into the
transmit/receive buffer register.
3822 GROUP USER’S MANUAL
2–115