3822_03 Datasheet, PDF (183/328 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O
sReceive operation in the UART mode
Receive operation in the UART mode is described below.
qStart of receive operation
In the receive enable state,^V1 set the receive enable bit (bit 5) of the serial I/O control register
(address 001A16) into the enabled state (“1”). With this operation, a start bit is detected and a
receive operation of serial data is started.
qReceive operation
ŒWith the lapse of a 1/2 period of the shift
clock from detection of the falling of the P44/
RxD pin input, the P44/RxD pin level is
checked. When it is “L” level, the bit is judged
as a start bit.
When it is “H” level, the bit is judged as
noise, so the receive operation is stopped,
being put into wait status for a start bit again.
Shift clock
RXD (Noise)
RXD (ST)
Each 1-bit data is read into the receive shift
register from the P44/RxD pin in synchroni-
zation with the rising of the shift clocks.
D1
P44/RXD
b0
D0
Receive shift register
ŽThe data after the detection of the start bit
enters first into the most significant bit of
the receive shift register. Each time 1-bit data
is received, the data of the receive shift regis-
ter is shifted by 1 bit toward the least signifi-
cant bit.
When a specified number of bits has been
input into the receive shift register, the data
of the receive shift register (address 001816)
are transferred to the receive buffer register
(address 001816).^V2V3
D4
P44/RXD
b0
D3 D2 D1 D0
Receive shift register
Receive shift register D7 D6 D5 D4 D3 _{D2 D1 D0}
Transfer receive data
[Address 1816] ^{Receive buffer register}
V1: Initialization of register or others for a receive operation. Refer to “2.5.4 Register setting exam-
ple.”
V2: When the data bit length is 7 bits, bits 0 to 6 of the receive buffer register are receive data, and
bit 7 (MSB) is cleared to “0.”
V3: When data remains without reading out the data of the receive buffer register (the receive buffer
full flag is “1”) and yet all the receive data has been input to the receive shift register, the overrun
error flag of the serial I/O status register is set to “1.” At this time, the data of the receive shift
register is not transferred to the receive buffer register, but the former data of the receive buffer
register is held.
3822 GROUP USER’S MANUAL
2–117