PD44164095B_15 Datasheet, PDF (8/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD44164095B, μPD44164185B
Power-On Sequence in DDR II SRAM
DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following timing charts show the recommended power-on sequence.
The following power-up supply voltage application is recommended: V_SS, V_DD, V_DDQ, V_REF, then V_IN. V_DD and
V_DDQ can be applied simultaneously, as long as V_DDQ does not exceed V_DD by more than 0.5 V during power-up.
The following power-down supply voltage removal sequence is recommended: V_IN, V_REF, V_DDQ, V_DD, V_SS. V_DD
and V_DDQ can be removed simultaneously, as long as V_DDQ does not exceed V_DD by more than 0.5 V during
power-down.
Power-On Sequence
Apply power and tie DLL# to HIGH.
- Apply V_DD before V_DDQ.
- Apply V_DDQ before V_REF or at the same time as V_REF.
Provide stable clock for more than 20 μs to lock the PLL.
PLL Constraints
The PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified as
TKC var. The PLL can cover 120 MHz as the lowest frequency. If the input clock is unstable and the PLL is
enabled, then the PLL may lock onto an undesired clock frequency.
Power-On Waveforms
VDD/VDDQ
DLL#
Clock
VDD/VDDQ Stable (< ±0.1 V DC per 50 ns)
Fix HIGH (or tied to VDDQ)
Unstable Clock
20 μs or more
Stable Clock
Normal Operation
Start
R10DS0016EJ0200 Rev.2.00
October 6, 2011
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