PD44164095B_15 Datasheet, PDF (27/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD44164095B, μPD44164185B
Output Pin States of CQ, CQ# and Q
Instructions
Control-Register Status
EXTEST
0
1
IDCODE
0
1
SAMPLE-Z
0
1
SAMPLE
0
1
BYPASS
0
1
Output Pin Status
CQ,CQ#
Q
Update
High-Z
Update
Update
SRAM
SRAM
SRAM
SRAM
High-Z
High-Z
High-Z
High-Z
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 107).
There are three statuses:
Update : Contents of the “Update Register” are output to the
output pin (DDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (DDR Pad).
High-Z :The output pin (DDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
Boundary Scan
Register
CAPTURE
Register
Update
Register
Update
SRAM
Output
DDR
Pad
High-Z
SRAM
SRAM
Output
Driver
High-Z
JTAG ctrl
R10DS0016EJ0200 Rev.2.00
October 6, 2011
Page 27 of 34