PD44164095B_15 Datasheet, PDF (13/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD44164095B, μPD44164185B
DC Characteristics 1 (TA = 0 to 70°C, V_DD = 1.8 ± 0.1 V)
Parameter
Symbol
Test condition
Input leakage current
I_LI
I/O leakage current
I_LO
Operating supply current I_DD
(Read cycle / Write cycle)
V_IN ≤ V_IL or V_IN ≥ V_IH,
I_I/O = 0 mA,
Cycle = MAX.
Standby supply current
(NOP)
Output HIGH voltage
Output LOW voltage
I_SB1 V_IN ≤ V_IL or V_IN ≥ V_IH,
I_I/O = 0 mA,
Cycle = MAX.
Inputs static
V_OH(Low) |I_OH| ≤ 0.1 mA
V_OH Note1
V_OL(Low) I_OL ≤ 0.1 mA
V_OL Note2
MIN.
−2
−2
-E33
-E35
-E40
-E50
-E33
-E35
-E40
-E50
V_DDQ−0.2
V_DDQ/2−0.12
V_SS
V_DDQ/2−0.12
MAX.
x9
x18
+2
+2
500 530
490 520
450 480
400 420
390 400
380 390
380 380
350 350
V_DDQ
V_DDQ/2+0.12
0.2
V_DDQ/2+0.12
Unit Note
μA
μA
mA
mA
V 3, 4
V 3, 4
V 3, 4
V 3, 4
Notes 1. Outputs are impedance-controlled. | I_OH | = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
2. Outputs are impedance-controlled. I_OL = (V_DDQ/2)/(RQ/5) ±15% for values of 175 Ω ≤ RQ ≤ 350 Ω.
3. AC load current is higher than the shown DC values.
4. HSTL outputs meet JEDEC HSTL Class I standards.
R10DS0016EJ0200 Rev.2.00
October 6, 2011
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