PD44164095B_15 Datasheet, PDF (4/35 Pages) Renesas Technology Corp – 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

μPD44164095B, μPD44164185B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD44164185B]
1M x 18
1
2
3
4
5
A CQ# VSS/144M NC/36M R, W# BW1#
B NC
Q9
D9
A
NC
C NC
NC
D10
VSS
A
D NC
D11 Q10
VSS
VSS
E NC
NC
Q11 VDDQ
VSS
F NC
Q12
D12 VDDQ
VDD
G NC
D13
Q13 VDDQ
VDD
H DLL# VREF VDDQ VDDQ
VDD
J NC
NC
D14
VDDQ
VDD
K NC
NC
Q14
VDDQ
VDD
L NC
Q15
D15 VDDQ
VSS
M NC
NC
D16
VSS
VSS
N NC
D17 Q16
VSS
A
P NC
NC
Q17
A
A
R TDO TCK
A
A
A
6
7
8
9
10
11
K# NC/288M LD#
A
VSS/72M CQ
K BW0# A
NC
NC
Q8
A
A
VSS
NC
Q7
D8
VSS
VSS
VSS
NC
NC
D7
VSS
VSS
VDDQ
NC
D6
Q6
VSS
VDD
VDDQ
NC
NC
Q5
VSS
VDD
VDDQ
NC
NC
D5
VSS
VDD
VDDQ VDDQ
VREF
ZQ
VSS
VDD
VDDQ
NC
Q4
D4
VSS
VDD
VDDQ
NC
D3
Q3
VSS
VSS
VDDQ
NC
NC
Q2
VSS
VSS
VSS
NC
Q1
D2
A
A
VSS
NC
NC
D1
C
A
A
NC
D0
Q0
C#
A
A
A
TMS TDI
A
D0 to D17
Q0 to Q17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V_REF
V_DD
V_DDQ
V_SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1.
2.
3.
×××# indicates active LOW.
Refer to Package Dimensions for the index mark.
2A, 3A, 7A and 10A are expansion addresses : 3A for 36Mb
: 3A and 10A for 72Mb
: 3A, 10A and 2A for 144Mb
: 3A, 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0016EJ0200 Rev.2.00
October 6, 2011
Page 4 of 34