SH74593_15 Datasheet, PDF (7/38 Pages) Renesas Technology Corp – RENESAS MCU

SH74593
Page
12-23
Description
• Figure 12.8 Procedure for Transition to ROM P/E Mode
Product Specifies “ROM P/E mode”
SH74562 To set FENTRY0 to 1 : Write H’AA01
SH74593 To set FENTRY1 to 1 : Write H’AA02
To set FENTRY0 to 1 : Write H’AA01
2. Details
12-24
12-25
Please refer to Appendix D.7.
• 12.6.3 FCU Command Usage : (2) Entering ROM Read Mode
Product Description
SH74562 To enable high-speed ROM read access over the SuperHyway bus, it is necessary to set the FCU
to ROM read mode by clearing the FENTRY0 bit in the FENTRYR register.
SH74593 To enable high-speed ROM read access over the SuperHyway bus, it is necessary to set the FCU
to ROM read mode by clearing bits FENTRY1 and FENTRY0 in the FENTRYR register.
• 12.6.3 FCU Command Usage : (3) Programming
Product Description
SH74562 The addresses that can be specified in the first to 131st cycles depend on the setting of the
FENTRY0 bit in the FENTRYR register. An address in the range from H'FD80 0000 to H'FD8F
FFFF is can be specified when the FENTRY0 bit is set to "1". If a command is issued while an
illegal combination of the FENTRY0 bit value and addresses is specified, the FCU detects an error
and enters command-locked state (see section 12.8.3, Error Protection).
12-33
SH74593 The addresses that can be specified in the first to 131st cycles depend on the setting of bits
FENTRY1 and FENTRY0 in the FENTRYR register. An address in the range from H'FD90 0000
to H'FD97 FFFF is can be specified when the FENTRY1 bit is set to "1", or an address in the
range from H'FD80 0000 to H'FD8F FFFF is can be specified when the FENTRY0 bit is set to "1".
If a command is issued while an illegal combination of FENTRY1 and FENTRY0 bit values and
addresses is specified, the FCU detects an error and enters command-locked state (see section
12.8.3, Error Protection).
• 12.8.1 Hardware Protection : (1) Protection through FWE Pin
Product Description
SH74562 In this state,"1" cannot be written to the FENTRY0 bit in the FENTRYR register; that is, ROM P/E
mode cannot be entered, which prevents the ROM from being programmed or erased.
When the FRDY bit is set to "1" and the FWE pin is "L" level, the FCU clears the FENTRY0 bit to
disable ROM programming and erasure.
12-33
SH74593 In this state,"1" cannot be written to bits FENTRY1 and FENTRY0 in the FENTRYR register; that
is, ROM P/E mode cannot be entered, which prevents the ROM from being programmed or
erased.
When the FRDY bit is set to "1" and the FWE pin is "L" level, the FCU clears bits FENTRY1 and
FENTRY0 to disable ROM programming and erasure.
• 12.8.2 Software Protection : (1) FENTRYR Protection
Product Description
SH74562 When the FENTRY0 bit is "0", the EB00 to EB19 blocks of ROM (read addresses: H'0000 0000 to
H'000F FFFF, program/erase addresses: H'FD80 0000 to H'FD8F FFFF) goes to ROM read mode.
SH74593 When the FENTRY1 bit in the FENTRYR register is "0", the EB20 to EB23 blocks of ROM
(read addresses: H'0010 0000 to H'0017 FFFF, program/erase addresses: H'FD90 0000 to
H'FD97 FFFF) goes to ROM read mode. When the FENTRY0 bit is "0", the EB00 to EB19 blocks
of ROM (read addresses: H'0000 0000 to H'000F FFFF, program/erase addresses: H'FD80 0000
to H'FD8F FFFF) goes to ROM read mode.
R01DS0186EJ0120 Rev.01.20
Sep 10, 2012
Page 7 of 35