SH74593_15 Datasheet, PDF (21/38 Pages) Renesas Technology Corp – RENESAS MCU

SH74593
Appendix D
Bit
0
After
Abbreviation Reset
FENTRY0 0
RW
Description
R W ROM P/E Mode Entry Bit 0
These bits specify the P/E mode for the EB00 to EB19 blocks of ROM
(read addresses: H'0000 0000 to H'000F FFFF; program/erase
addresses: H'FD80 0000 to H'FD8F FFFF).
0: The block of ROM from EB00 to EB19 (1Mbyte) is in read mode
1: The block of ROM from EB00 to EB19 (1Mbyte) is in P/E mode
Programming is enabled when the following conditions are all satisfied:
• The FWE bit in the FPMON register is "1".
• The FRDY bit in the FSTATR0 register is "1".
• H'AA is written to the FEKEY bit in word access.
[Conditions for clearing to "0"]
• The FRDY bit in the FSTATR0 register becomes "1" and the FWE bit
in the FPMON register becomes "0".
• This register is written to in byte access.
• A value other than H'AA is written to the FEKEY bit in word access.
• "0" is written to the FENTRY0 bit while the write enabling conditions
are satisfied.
• The FENTRYR register is written to while the FENTRYR register is
not H'0000 and the write enabling conditions are satisfied.
[Condition for setting to "1"]
• "1" is written to FENTRY0 while the write enabling conditions are
satisfied and the FENTRYR register is H'0000.
R01DS0186EJ0120 Rev.01.20
Sep 10, 2012
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