SH74593_15 Datasheet, PDF (20/38 Pages) Renesas Technology Corp – RENESAS MCU

SH74593
Appendix D
Appendix D.4
12.3.6 Flash P/E Mode Entry Register (FENTRYR)
The FENTRYR register specifies the P/E mode for the ROM. Writing to the FENTRYR register is enabled only when a
specified value is written to the high-order byte. Writing any other value initializes this register. To specify the P/E
mode for the ROM so that the FCU can accept commands, set either of bits FENTRY1 and FENTRY0 to "1". Note
that if this register is set to a value other than H'0001 or H'0002, the ILGLERR bit in the FSTATR0 register will be set
to "1" and the FCU will switch to the command-locked state.
The FENTRYR register can be initialized by a hardware reset, or setting the FRESET bit in the FRESETR register to
"1".
Flash P/E Mode Entry Register (FENTRYR)
<P4 address: location H'FDFF A902>
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FEKEY
⎯
⎯
⎯
⎯
⎯
⎯
FENT FENT
RY1 RY0
After Reset: ⁰
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 to 8
7 to 2
1
After
Abbreviation Reset
FEKEY
All 0
⎯
All 0
FENTRY1 0
<After Reset: H'0000>
RW
Description
0 W FENTRYR Register Write Key Code Bits
These bits enable or disable bit modification of FENTRY1 and
FENTRY0. The data written to these bits are not retained. These bits are
always read as "0".
H'AA: Enable bit modification of FENTRY1 and FENTRY0.
Other than H'AA: Disable bit modification of FENTRY1 and FENTRY0.
0 0 Reserved Bits
These bits are always read as "0". The write value should always be "0".
R W ROM P/E Mode Entry Bit 1
These bits specify the P/E mode for the EB20 to EB23 blocks of
ROM (read addresses: H'0010 0000 to H'0017 FFFF; program/erase
addresses: H'FD90 0000 to H'FD97 FFFF).
0: The block of ROM from EB20 to EB23 (0.5Mbytes) is in read mode
1: The block of ROM from EB20 to EB23 (0.5Mbytes) is in P/E mode
Programming is enabled when the following conditions are all
satisfied:
• The FWE bit in the FPMON register is "1".
• The FRDY bit in the FSTATR0 register is "1".
• H'AA is written to the FEKEY bit in word access.
[Conditions for clearing to "0"]
• The FRDY bit in the FSTATR0 register becomes "1" and the FWE
bit in the FPMON register becomes "0".
• This register is written to in byte access.
• A value other than H'AA is written to the FEKEY bit in word
access.
• "0" is written to FENTRY1 while the write enabling conditions
are satisfied.
• The FENTRYR register is written to while the FENTRYR register
is not H'0000 and the write enabling conditions are satisfied.
[Condition for setting to "1"]
• "1" is written to the FENTRY1 bit while the write enabling
conditions are satisfied and the FENTRYR register is H'0000.
R01DS0186EJ0120 Rev.01.20
Sep 10, 2012
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