SH74593_15 Datasheet, PDF (19/38 Pages) Renesas Technology Corp – RENESAS MCU

SH74593
Appendix D
After
Bit Abbreviation Reset R W
Description
4
CMDLK
0
R ⎯ FCU Command Lock Bit
Indicates whether the FCU is in command-locked state (see section
12.8.3, Error Protection).
0: The FCU is not in a command-locked state
1: The FCU is in a command-locked state
[Condition for clearing to "0"]
• The FCU completes the status-clear command processing while the
FASTAT register is H'10.
[Condition for setting to "1"]
• The FCU detects an error and enters command-locked state.
3 to 0
⎯
All 0
0 0 Reserved Bits
These bits are always read as "0". The write value should always be "0".
Note: *1 Writing a "0" after reading a "1" is only allowed in order to clear the flag.
R01DS0186EJ0120 Rev.01.20
Sep 10, 2012
Page 19 of 35