M32C8B_09 Datasheet, PDF (65/69 Pages) Renesas Technology Corp – RENESAS MCU

M32C/8B Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
Read Timing (1φ + 1φ Bus Cycle)
BCLK
VCC1=VCC2=3.3V
CSi
ADi
BHE
RD
td(BCLK-CS)
18ns.max⁽¹⁾
tcyc
td(BCLK-AD)
18ns.max⁽¹⁾
td(BCLK-RD)
18ns.max
tac1(RD-DB)⁽²⁾
th(BCLK-CS)
0ns.min
th(RD-CS)
0ns.min
th(BCLK-AD)
0ns.min
th(RD-AD)
0ns.min
th(BCLK-RD)
-3ns.min
tac1(AD-DB)⁽²⁾
DBi
Hi-Z
tsu(DB-BCLK)
27ns.min⁽¹⁾
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle aφ + bφ, n = a + b)
Write Timing (1φ + 1φ Bus Cycle)
BCLK
td(BCLK-CS)
18ns.max⁽¹⁾
CSi
th(BCLK-CS)
0ns.min
ADi
BHE
tcyc
td(BCLK-AD)
18ns.max⁽¹⁾
td(BCLK-WR)
18ns.max
WR,WRL,WRH
tw(WR)⁽³⁾
td(DB-WR)⁽³⁾
th(WR-CS)⁽³⁾
th(BCLK-AD)
0ns.min
th(WR-AD)⁽³⁾
th(BCLK-WR)
0ns.min
th(WR-DB)⁽³⁾
DBi
NOTES:
3. Varies with operation frequency:
td(DB-WR) = (tcyc x m - 20) ns.min
( if external bus cycle aφ + bφ, m = b)
th(WR-DB) = (tcyc / 2 - 15) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
( if external bus cycle aφ + bφ, n = (b x 2) - 1)
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
tcyc=
10⁹
f(BCLK)
Figure 5.9 VCC1 = VCC2 = 3.3 V Timing Diagram (3)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 65 of 67