M32C8B_09 Datasheet, PDF (61/69 Pages) Renesas Technology Corp – RENESAS MCU

M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.48 Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
tw(WR)
Parameter
Measurement
Condition
Standard
Min.
Max.
Unit
Address output delay time
18
ns
Address output hold time (BCLK standard)
0
ns
Address output hold time (RD standard)⁽³⁾
0
ns
Address output hold time (WR standard)⁽³⁾
(note 1)
ns
Chip-select signal output delay time
18
ns
Chip-select signal output hold time (BCLK standard)
0
ns
Chip-select signal output hold time (RD standard)⁽³⁾
0
ns
Chip-select signal output hold time (WR standard)⁽³⁾ See Figure 5.2 (note 1)
ns
RD signal output delay time
18
ns
RD signal output hold time
-3
ns
WR signal output delay time
18
ns
WR signal output hold time
0
ns
Data output delay time (WR standard)
(note 2)
ns
Data output hold time (WR standard)⁽³⁾
(note 1)
ns
WR output width
(note 2)
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
10⁹
th(WR-DB) =
- 15 [ns]
f(BCLK) × 2
10⁹
th(WR-AD) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-CS) =
- 10 [ns]
f(BCLK) × 2
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR) =
10⁹ × m
f(BCLK)
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
tw(WR)
10⁹ × n
=
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
f(BCLK) × 2
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 61 of 67