M32C8B_09 Datasheet, PDF (46/69 Pages) Renesas Technology Corp – RENESAS MCU

M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.27 Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)⁽³⁾
Address output hold time (WR standard)⁽³⁾
-3
ns
0
ns
(note 1)
ns
td(BCLK-CS) Chip-select signal output delay time
18
ns
th(BCLK-CS) Chip-select signal output hold time (BCLK standard)
-3
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)⁽³⁾
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)⁽³⁾ See Figure 5.2 (note 1)
ns
td(BCLK-RD) RD signal output delay time
18
ns
th(BCLK-RD) RD signal output hold time
-5
ns
td(BCLK-WR) WR signal output delay time
18
ns
th(BCLK-WR) WR signal output hold time
-5
ns
td(DB-WR)
th(WR-DB)
Data output delay time (WR standard)
Data output hold time (WR standard)⁽³⁾
(note 2)
ns
(note 1)
ns
tw(WR)
WR output width
(note 2)
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
10⁹
th(WR-DB) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-AD) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-CS) =
- 10 [ns]
f(BCLK) × 2
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR) =
10⁹ × m
f(BCLK)
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
tw(WR)
10⁹ × n
=
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
f(BCLK) × 2
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 46 of 67