M32C8B_09 Datasheet, PDF (45/69 Pages) Renesas Technology Corp – RENESAS MCU

M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.26 Memory Expansion mode and Microprocessor Mode
Symbol
tac1(RD-DB)
tac1(AD-DB)
tac2(RD-DB)
tac2(AD-DB)
Parameter
Data input access time (RD standard)
Data input access time (AD standard, CS standard)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
Standard
Unit
Min.
Max.
(note 1) _ns
(note 1) _ns
(note 1) _ns
(note 1) ns
tsu(DB-BCLK) Data input setup time
tsu(RDY-BCLK) _{RDY input setup time}
tsu(HOLD-BCLK) _{HOLD input setup time}
th(RD-DB)
Data input hold time
th(BCLK-RDY) _{RDY input hold time}
th(BCLK-HOLD) _{HOLD input hold time}
26
ns
26
ns
30
ns
0
ns
0
ns
0
ns
td(BCLK-HLDA) _{HLDA output delay time}
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
10⁹ × m
tac1(RD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
f(BCLK) × 2
tac1(AD-DB) =
10⁹ × n
f(BCLK)
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
10⁹ × m
tac2(RD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
f(BCLK) × 2
10⁹ × p
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
f(BCLK) × 2
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 45 of 67