M32C8B_09 Datasheet, PDF (62/69 Pages) Renesas Technology Corp – RENESAS MCU

M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.49 Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space with multiplexed bus)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Max.
Unit
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)⁽⁵⁾
(note 1)
ns
th(WR-AD)
Address output hold time (WR standard)⁽⁵⁾
(note 1)
ns
td(BCLK-CS) Chip-select signal output delay time
18
ns
th(BCLK-CS) Chip-select signal output hold time (BCLK standard)
0
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)⁽⁵⁾
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)⁽⁵⁾
(note 1)
ns
td(BCLK-RD) RD signal output delay time
18
ns
th(BCLK-RD) RD signal output hold time
See Figure 5.2 -3
ns
td(BCLK-WR) WR signal output delay time
18
ns
th(BCLK-WR) WR signal output hold time
0
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)⁽⁵⁾
(note 1)
ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
18
ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
-2
ns
td(AD-ALE)
ALE signal output delay time (address standard)
(note 3)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(note 4)
ns
tdz(RD-AD)
Address output float start time
8
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
10⁹
th(RD-AD) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-AD) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(RD-CS) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-CS) =
- 10 [ns]
f(BCLK) × 2
10⁹
th(WR-DB) =
- 15 [ns]
f(BCLK) × 2
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
10⁹ × m
td(DB-WR) =
- 25 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
f(BCLK) × 2
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) =
10⁹ × n
- 20 [ns] (if external bus cycle is aφ + bφ, n = a)
f(BCLK) × 2
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) =
10⁹ × n
- 10 [ns] (if external bus cycle is aφ + bφ, n = a)
f(BCLK) × 2
5. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 62 of 67