H8SX1650 Datasheet, PDF (555/692 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 A/D Converter
ADIE
ADST
Set*
Set*
A/D conversion start
ADF
Clear*
Set*
Clear*
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Waiting for conversion
Waiting for
conversion
A/D conversion 1
Channel 2 (AN2)
operation state
Waiting for conversion
Channel 3 (AN3)
operation state
Waiting for conversion
ADDRA
ADDRB
ADDRC
Waiting for conversion A/D conversion 2
Waiting for conversion
Reading A/D conversion result
A/D conversion result 1
Reading A/D conversion result
A/D conversion result 2
ADDRD
Note: * ↓ indicates the timing of instruction execution by software.
Figure 14.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
14.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified
channels up to four or eight channels.
1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on
a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight
channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is
performed on four channels, A/D conversion starts on AN4 when CH3 and CH2 = B'01. When
consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0
when CH3 = B'0.
2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.
Rev.2.00 Jun. 28, 2007 Page 533 of 666
REJ09B0311-0200