H8SX1650 Datasheet, PDF (243/692 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 7 Data Transfer Controller (DTC)
7.2.2 DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit
7
Bit Name
CHNE
Initial Value Undefined
R/W

6
CHNS
Undefined

5
DISEL
Undefined

4
DTS
Undefined

3
DM1
Undefined

2
DM0
Undefined

1

Undefined

0

Undefined

Initial
Bit Bit Name Value
R/W Description
7
CHNE
Undefined 
DTC Chain Transfer Enable
Specifies the chain transfer. For details, see 7.5.7, Chain
Transfer. The chain transfer condition is selected by the
CHNS bit.
0: Disables the chain transfer
1: Enables the chain transfer
6
CHNS
Undefined 
DTC Chain Transfer Select
Specifies the chain transfer condition. If the following
transfer is a chain transfer, the completion check of the
specified transfer count is not performed and activation
source flag or DTCER is not cleared.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
5
DISEL
Undefined 
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends. When
this bit is set to 0, a CPU interrupt request is only
generated when the specified number of data transfer
ends.
4
DTS
Undefined 
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Rev.2.00 Jun. 28, 2007 Page 221 of 666
REJ09B0311-0200