H8SX1650 Datasheet, PDF (406/692 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.7 Conflict between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the write data.
Figure 9.49 shows the timing in this case.
Pφ
Address
Write
Compare match
signal
Buffer register
TGR write cycle
T₁
T₂
Buffer register
address
Data written to buffer register
N
M
TGR
M
Figure 9.49 Conflict between Buffer Register Write and Compare Match
9.9.8 Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 9.50 shows the timing in this case.
Rev.2.00 Jun. 28, 2007 Page 384 of 666
REJ09B0311-0200