H8SX1650 Datasheet, PDF (138/692 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 5 Interrupt Controller
Table 5.7 shows the CPU priority control.
Table 5.7 CPU Priority Control
Interrupt
Control Interrupt
Mode Priority
0
Default
2
IPR setting
Interrupt
Mask Bit
I = any
I=0
I=1
I2 to I0
Control Status
IPSETE in
CPUPCR CPUP2 to CPUP0
Updating of CPUP2
to CPUP0
0
B'111 to B'000
Enabled
1
B'000
Disabled
B'100
0
B'111 to B'000
Enabled
1
I2 to I0
Disabled
Table 5.8 shows a setting example of the priority control function over the DTC and the transfer
request control state.
Table 5.8 Example of Priority Control Function Setting and Control State
Interrupt Control CPUPCE in
Mode
CPUPCR
0
0
1
2
0
1
CPUP2 to
CPUP0
Any
B'000
B'100
B'100
B'100
B'000
Any
B'000
B'000
B'011
B'100
B'101
B'110
B'111
B'101
B'101
DTCP2 to
DTCP0
Any
B'000
B'000
B'000
B'111
B'111
Any
B'000
B'011
B'011
B'011
B'011
B'011
B'011
B'011
B'110
Transfer Request Control State
DTC
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Masked
Masked
Masked
Masked
Masked
Enabled
Rev.2.00 Jun. 28, 2007 Page 116 of 666
REJ09B0311-0200