H8SX1650 Datasheet, PDF (222/692 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 6 Bus Controller (BSC)
(1) Consecutive Reads in Different Areas
If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDSELn in IDLCR is cleared to 0, or bits
IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read
cycle (n = 0 to 7).
Figure 6.34 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data conflict is prevented.
Bus cycle A Bus cycle B
T₁
T₂
T₃
T₁
T₂
Bφ
Bus cycle A
Bus cycle B
T₁ T₂ T₃ T_i
T₁ T₂
Address bus
CS (area A)
CS (area B)
RD
Data bus
Data hold time is long
Data conflict
(a) No idle cycle inserted
(IDLS1 = 0)
(b) Idle cycle inserted
(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 6.34 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)
Rev.2.00 Jun. 28, 2007 Page 200 of 666
REJ09B0311-0200