TLK2211 Datasheet, PDF (5/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2211
www.ti.com ................................................................................................................................................................ SLLS873B – MAY 2008 – REVISED JULY 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
GND
1, 14, 21, 25,
33, 46
Ground
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
GNDPLL
64
Ground PLL ground. Provides a ground for the PLL circuitry.
DETAILED DESCRIPTION
DATA TRANSMISSION
This device supports the standard 10-bit interface (TBI) parallel bus.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0-TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
TRANSMISSION LATENCY
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times.
10 Bit Code
TXP, TXN
b9
t_{d(Tx latency)}
TD(0−9)
10 Bit Code
REFCLK
Figure 1. Transmitter Latency Full Rate Mode
DATA RECEPTION
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0, RBC1).
RECEIVER CLOCK SELECT MODE
There is only one mode of operation for the parallel busses that is the 10-bit (TBI) mode. In TBI mode, the
supported clock mode is half-rate clocks on RBC0 and RBC1. Table 1.
RBCMODE
0
Table 1. Mode Selection
MODE
TBI half-rate
FREQUENCY
(TLK2211)
60–130 MHz
In this mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half
the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with
respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel bytes using
the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data valid on the
rising edge of RBC1. See the timing diagram shown in Figure 2.
Copyright © 2008, Texas Instruments Incorporated
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