TLK2211 Datasheet, PDF (4/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2211
SLLS873B – MAY 2008 – REVISED JULY 2008 ................................................................................................................................................................ www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit
output data on RD0-RD9. The operation of these clocks is dependent upon the receive clock mode
selected.
RBC0
RBC1
31
30
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and
O RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect.
The clocks are always expanded during data realignment and never slivered or truncated. RBC0
registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is
aligned to the rising edge.
RBCMODE
32
I
P/D ⁽¹⁾
RBCMODE must be help low for normal operation.
SYNCEN.
I Synchronous function enable. When SYNCEN is high, the internal synchronization function is
24
P/U⁽²⁾ activated. When this function is activated, the transceiver detects the K28.5 comma character
(0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.
SYNC/PASS
47
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in
O
the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In
PRBS test mode (PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results
(high=pass).
LOS
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
26
O
If magnitude of RXP–RXN > 150 mV, LOS = 1, valid input signal
If magnitude of RXP–RXN < 150 mV and >50 mV, LOS is undefined
If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal
TEST
LOOPEN
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
19
I (P/D) capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
TCK
49
I Test clock. IEEE1149.1 (JTAG)
JTDI
48
I (P/D) Test data input. IEEE1149.1 (JTAG)
JTDO
27
O Test data output. IEEE1149.1 (JTAG)
JTRSTN
56
I
P/U⁽²⁾
Reset signal. IEEE1149.1 (JTAG)
JTMS
55
I
P/U⁽²⁾
Test mode select. IEEE1149.1 (JTAG)
ENABLE
I When this terminal is low, the device is disabled for Iddq testing. RD0 - RD9, RBCn, TXP, and
28
P/U⁽²⁾ TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
PRBSEN
I PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
16
P/D⁽¹⁾ verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
TESTEN
17
I
P/D⁽¹⁾
Manufacturing test terminal
POWER
VDD
5, 10, 20, 23,
29, 37, 42, Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
50, 63
VDDA
53, 57, 59, Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter.
60
VDDPLL
18
Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
GROUND
GNDA
15, 51,58 Ground Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.
(1) P/D = Internal pulldown
(2) P/U = Internal pullup
4
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