PD64A_15 Datasheet, PDF (44/66 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR INFRARED REMOTE CONTROL TRANSMISSION

µPD64A, 65
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD64A (ROM: 1K steps): Page 0
µPD65 (ROM: 2K steps): Pages 0, 1
µPD6P5 (PROM: 2K steps): Pages 0, 1
JMP addr
<1> Instruction code: page 0 0 1 0 0 0 1 0 0 0 1 , page 1 0 1 0 0 1 1 0 0 0 1
<2> Cycle count:
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1
<3> Function:
PC ← addr
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
a0).
JC addr
<1> Instruction code: page 0 0 1 1 0 0 1 0 0 0 1 , page 1 0 1 0 1 0 1 0 0 0 1
<2> Cycle count:
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1
<3> Function:
If CY = 1 PC ← addr
else PC ← PC + 2
If the carry flag CY is set (1), a jump is made to the address specified with addr (a9 to a0).
JNC addr
<1> Instruction code: page 0 0 1 1 0 1 1 0 0 0 1 , page 1 0 1 0 1 1 1 0 0 0 1
<2> Cycle count:
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1
<3> Function:
If CY = 0 PC ← addr
else PC ← PC + 2
If the carry flag CY is cleared (0), a jump is made to the address specified with addr (a9 to a0).
JF addr
<1> Instruction code: page 0 0 1 1 1 0 1 0 0 0 1 , page 1 1 0 0 0 0 1 0 0 0 1
<2> Cycle count:
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1
<3> Function:
If F = 1 PC ← addr
else PC ← PC + 2
If the status flag F is set (1), a jump is made to the address specified with addr (a9 to a0).
JNF addr
<1> Instruction code: page 0 0 1 1 1 1 1 0 0 0 1 , page 1 1 0 0 0 1 1 0 0 0 1
<2> Cycle count:
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
1
<3> Function:
If F = 0 PC ← addr
else PC ← PC + 2
If the status flag F is cleared (0), a jump is made to the address specified with addr (a9 to a0).
42
Data Sheet U14380EJ3V0DS00