PD64A_15 Datasheet, PDF (26/66 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR INFRARED REMOTE CONTROL TRANSMISSION

µPD64A, 65
Table 5-3. Standby Mode Setting (HALT #b3b2b1b0B) and Release Conditions
Operand Value of
HALT Instruction
b3
b2
b1
b0
0
0
0
0
0
1
1
1
1
0
1 Any combination of
b2b1b0 above
0/1
1
0
1
Setting Mode
Precondition for Setting
Release Conditions
STOP
STOP
STOP^{Note 1}
STOP
HALT
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
The KI/O0 pin is high-level output.
High level is input to at least one
of KI pins.
[The following conditions are added in addition to the above.]
—
High level is input to at least one
of S0, S1 and S2 pins^{Note 2}.
—
When the timer’s down counter is 0
Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an
internal reset takes effect at the time of program runaway.
2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby) must be specified as
follows.
S0, S1 pins: Input mode (specified by bits 0 and 2 of the P4 register)
S2 pin:
Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
enters STOP mode only after all the 10 bits of the timer’s down counter and the timer output
enable flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
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Data Sheet U14380EJ3V0DS00