PD64A_15 Datasheet, PDF (25/66 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR INFRARED REMOTE CONTROL TRANSMISSION

µPD64A, 65
5.2 Standby Mode Setting and Release
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the
standby mode to be set, the status flag (F) is required to have been cleared (0).
The standby mode is released by the release condition specified with the reset (POC) or the operand of the HALT
instruction. If the standby mode is released, the status flag (F) is set (1).
Even when the HALT instruction is executed in a state in which the status flag (F) is set (1), the standby mode
is not set. If the release condition is not met at this time, the status flag is cleared (0). If the release condition is
met, the status flag remains set (1).
Even in the case when the release condition has already been met at the point that the HALT instruction is
executed, the standby mode is not set. Here, also, the status flag (F) is set (1).
Caution Note that depending on the status of the status flag (F), the HALT instruction may not be
executed. For example, when setting HALT mode after checking the key status with the STTS
instruction, the system does not enter HALT mode as long as the status flag (F) remains set
(1), sometimes resulting in an unintended operation. In this case, the intended operation can
be realized by executing the STTS instruction immediately after setting the timer to clear (0)
the status flag.
Example STTS #03H
;To check the KI pin status
MOV
STTS
HALT
T, #0xxH ;To set the timer
#05H
;To clear the status flag
(During this time, be sure not to execute an instruction that may set the status flag.)
#05H
;To set HALT mode
Table 5-2. Addresses Executed After Standby Mode Release
Release Condition
Reset
Release condition shown in Table 5-3
Address Executed After Release
0 address
The address following the HALT instruction
Data Sheet U14380EJ3V0DS00
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