4507 Datasheet, PDF (39/115 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4507 Group
RAM BACK-UP MODE
The 4507 Group has the RAM back-up mode.
When the POF2 instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
The POF2 instruction is equal to the NOP instruction when the
EPOF instruction is not executed before the POF2 instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 15 shows the function and states retained at RAM back-up.
Figure 37 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF instruction and
POF2 instruction continuously, the CPU starts executing the pro-
gram from address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
In this case, the P flag is “0.”
Table 15 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Selected oscillation circuit
Timer control register W1
Timer control registers W2, W6
Clock control register MR
Interrupt control registers V1, V2
Interrupt control register I1
Timer 1 function
Timer 2 function
A/D conversion function
A/D control register Q1
Pull-up control registers PU0 to PU2
Key-on wakeup control registers K0 to K2
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
RAM back-up
✕
O
(Note 5)
O
✕
O
✕
✕
O
✕
(Note 3)
✕
O
O
O
✕
✕
Timer 2 interrupt request flag (T2F)
Watchdog timer flags (WDF1)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
A/D conversion completion flag (ADF)
Interrupt enable flag (INTE)
(Note 3)
✕ (Note 4)
✕
✕ (Note 4)
✕
✕
Notes 1:“O” represents that the function can be retained, and “✕” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then execute the POF2 instruction.
5: As for the D2/C pin, the output latch of port C is set to “1” at the
RAM back-up. However, the output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM
back-up.
Rev.3.01 2005.02.04 page 39 of 111
REJ03B0107-0301