4507 Datasheet, PDF (19/115 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4507 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The A/D interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruc-
tion. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
at RAM back-up : 00002
R/W
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
Interrupt control register V2
at reset : 00002
at RAM back-up : 00002
0
V23
Not used
1
0
V22
A/D interrupt enable bit
1
0
V21
Not used
1
0
V20
Not used
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instrucion.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
R/W
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10, V12, V13, V22), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are sat-
isfied on execution of other than one-cycle instructions (Refer to
Figure 16).
Rev.3.01 2005.02.04 page 19 of 111
REJ03B0107-0301