HN58V256A Datasheet, PDF (18/25 Pages) Hitachi Semiconductor – 256k EEPROM (32-kword x 8-bit) Ready/Busy and RES function (HN58V257A)

HN58V256A Series, HN58V257A Series
2. Data Protection at V_CC On/Off
When V_CC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
Note: The EPROM should be kept in unprogrammable state during V_CC on/off by using CPU RESET signal.
V_CC
CPU
RESET
* _{Unprogrammable}
* _{Unprogrammable}
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the
table below.
CE
V_CC
×
×
OE
×
V_SS
×
WE
×
×
V_CC
×: Don’t care.
V_CC: Pull-up to V_CC level.
V_SS: Pull-down to V_SS level.
2.2 Protection by RES (only the HN58V257A series)
The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the
EEPROM’s RES pin. RES should be kept V_SS level during V_CC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming
operation doesn’t finish correctly in case that RES falls low during programming operation. RES
should be kept high for 10 ms after the last data input.
V_CC
4-5
9-
or +-
Program inhibit
1 µs min 100 µs min
Program inhibit
10 ms min
Rev.5.00, Nov. 17.2003, page 18 of 22