HYB39SC128800FE Datasheet, PDF (9/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
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70
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UHJDGGU
Z
Z
Z
Z
03%6
Field
BL
Bits
Type
[2:0]
w
BT
3
CL
[6:4]
TM
[8:7]
WBL
—
9
[12:10]
Description
TABLE 5
Mode Register Definition (BA[1:0] = 00_B)
Burst Length
Number of sequential bits per DQ related to one read/write command, see
Table 6.
Note: All other bit combinations are RESERVED
000_B 1
001_B 2
010_B 4
011_B 8
111_B Full Page (Sequential burst type only)
Burst Type
0_B Sequential
1_B Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010_B 2
011_B 3
Test Mode
Note: All other bit combinations are RESERVED.
00_B Mode register set
Write Burst Length
0_B Burst write
1_B Single bit write
Reserved, set to zero
Burst Length Starting Column Address
A2
A1
A0
2
—
—
0
—
—
1
TABLE 6
Burst Length and Sequence
Order of Accesses Within a Burst
Type=Sequential
0–1
1–0
Type=Interleaved
0–1
1–0
Rev. 1.1, 2007-02
9
09072006-N4GC-EREN