HYB39SC128800FE Datasheet, PDF (13/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Symbol Test Condition
TABLE 11
I_DD Specifications and Conditions
–6 –7 Unit Note ¹⁾
I_DD1
I_DD2P
I_DD2N
I_DD3N
I_DD3P
I_DD4
I_DD5
I_DD6
t_RC = t_RC(min), I_O = 0 mA
CS =V_{IH (min.)}, CKE ≤V_IL(max)
CS =V_{IH (min.)}, CKE≥ V_IH(min)
CS = V_IH(min), CKE ≥V_IH(min.)
CS = V_IH(min), CKE ≤ V_IL(max.)
—
t_RFC= t_RFC(min)
t_RFC= 15.6 µs
—
100 80 mA
2
2
mA
26 22 mA
40 35 mA
5
5
mA
65 57 mA
168 142 mA
25 25 mA
3
3
mA
0.8 0.8 mA
2)3)
1)
1)
1)
1)
1)3)
4)
Standard components
Low power components , at 85 °C
1) V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V, T_A see Table 7
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed
once during t_CK.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and
the V_DDQ current is excluded.
4) t_RFC= t_RFC(min) “burst refresh”, t_RFC= 15.6 µs “distributed refresh”.
4.2
AC Characteristics
Parameter
Clock and Clock Enable
Clock Frequency
Access Time from Clock
Clock High Pulse Width
Clock Low Pulse Width
Transition time
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
Rev. 1.1, 2007-02
09072006-N4GC-EREN
Symbol
TABLE 12
AC Timing - Absolute Specifications
–7
PC133–222
–6
PC166–333
Unit Note¹⁾²⁾
3)
Min. Max. Min. Max.
t_CK
—
–7
—
–6
ns CL3
—
–7.5
—
–7.5 ns CL2
t_AC
—
5.4
—
5.4
ns CL3
—
5.4
—
5.4
ns CL2
3)4)5)
t_CH
2.5 —
2
—
ns
t_CL
2.5 —
2
—
ns
t_T
0.3 1.2
0.3
1.2
ns
t_IS
1.5 —
1.5
—
ns
6)
t_IH
0.8 —
0.8
—
ns
6)
t_CK
1.5 —
1.5
—
ns
6)
13