HYB39SC128800FE Datasheet, PDF (11/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
4
Electrical Characteristics
4.1
Operating Conditions
Parameter
Input / Output voltage relative to V_SS
Voltage on V_DD supply relative to V_SS
Voltage on V_DDQ supply relative to V_SS
Operating Temperature for HYB...
Operating Temperature for HYI...
Storage temperature range
Power dissipation per SDRAM component
Data out current (short circuit)
Symbol
V_IN, V_OUT
V_DD
V_DDQ
T_A
T_A
T_STG
P_D
I_OUT
Limit Values
Min.
–1.0
–1.0
–1.0
0
–40
–55
—
—
Max.
+4.6
+4.6
+4.6
+70
+85
+150
1
50
TABLE 7
Absolute Maximum Ratings
Unit Note/
Test Condition
V
—
V
—
V
—
°C
—
°C
—
°C
—
W
—
mA
—
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated
circuit.
TABLE 8
DC Characteristics
Parameter
Symbol
Values
Min.
Max.
Unit Note/
Test Condition
Supply Voltage
V_DD
3.0
3.6
V
1)
I/O Supply Voltage
V_DDQ
3.0
3.6
V
1)
Input high voltage
V_IH
2.0
V_DDQ + 0.3 V
1)2)
Input low voltage
V_IL
–0.3
+0.8
V
1)2)
Output high voltage (I_OUT = – 4.0 mA)
V_OH
2.4
—
V
1)
Output low voltage (I_OUT = 4.0 mA)
V_OL
—
0.4
V
1)
Input leakage current, any input
I_IL
–5
+5
µA
—
(0 V < V_IN < V_DD, all other inputs = 0 V)
Output leakage current
I_OL
–5
+5
µA
—
(DQs are disabled, 0 V < V_OUT < V_DDQ)
1) All voltages are referenced to V_SS
2) V_IH may overshoot to V_DDQ + 2.0 V for pulse width of < 4ns with 3.3 V. V_IL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V.
Pulse width measured at 50 % points with amplitude measured peak to DC reference.
Rev. 1.1, 2007-02
11
09072006-N4GC-EREN