HYB39SC128800FE Datasheet, PDF (12/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Parameter
TABLE 9
Input and Output Capacitances
Symbol Values
Unit Note
Min. Max.
Input Capacitances: CK, CK
Input Capacitance
(A0-A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)
C_I1
2.5 3.5
pF
1)2)
C_I2
2.5 3.8
pF
1)2)
Input/Output Capacitance (DQ)
C_I0
4.0 6.0
pF
1)2)
1) V_DD,V_DDQ = 3.3 V ± 0.3 V, f = 1 MHz, T_A see Table 7
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
Parameter
Operating Current
Precharge Standby Current
No Operating Current
Burst Operating Current
Auto Refresh Current
Self Refresh Current
One bank active, Burst length = 1
Power down mode
Non-power down mode
Active state (max. 4 banks)
Read command cycling
Auto Refresh command cycling
Self Refresh Mode, CKE=0.2 V, t_CK=infinity
TABLE 10
I_DD Conditions
Symbol
I_DD1
I_DD2P
I_DD2N
I_DD3N
I_DD3P
I_DD4
I_DD5
I_DD6
Rev. 1.1, 2007-02
12
09072006-N4GC-EREN