HYB39SC128800FE Datasheet, PDF (14/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
Parameter
Symbol
–7
PC133–222
–6
PC166–333
Unit Note¹⁾²⁾
3)
Min. Max. Min. Max.
CKE Hold Time
Mode Register Set-up to Active delay
Power Down Mode Entry Time
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto Refresh
Activate(a) to Activate(b) Command period
CAS(a) to CAS(b) Command period
Refresh Cycle
t_CKH
0.8 —
0.8
—
ns
6)
t_RSC
2
—
2
—
t_CK
t_SB
0
7
0
6
ns
t_RCD
15
—
15
—
ns
7)
t_RP
15
—
15
—
ns
7)
t_RAS
37
100k 36
100k ns
7)
t_RC
60
—
60
—
ns
7)
t_RFC
63
—
60
—
ns
t_RRD
14
—
12
—
ns
7)
t_CCD
1
—
1
—
t_CK
Refresh Period (4096 cycles)
Self Refresh Exit Time
Data Out Hold Time
Read Cycle
t_REF
t_SREX
t_OH
–
64
1
—
3
—
–
64
1
—
2.5
—
ms
t_CK
ns
3)5)
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
Write Cycle
Last Data Input to Precharge
(Write without Auto Precharge)
Last Data Input to Activate
(Write with Auto Precharge)
t_LZ
t_HZ
t_DQZ
0
—
3
7
—
2
t_WR
14
—
t_DAL(min.)
—
—
0
—
3
6
—
2
12
—
—
—
ns
ns
t_CK
ns
8)
t_CK
9)
DQM Write Mask Latency
t_DQW
0
—
0
—
t_CK
1) T_A = 0 to 70 °C; V_SS = 0 V; V_DD, V_DDQ = 3.3 V ± 0.3 V, t_T = 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have V_IL = 0.4 V and V_IH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition
time is measured between V_IH and V_IL. All AC measurements assume t_T = 1 ns with the AC output load circuit shown in figure below.
Specified t_AC and t_OH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge
rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (t_T/2 - 0.5) ns has to be added to this parameter.
5) Access time from clock t_ac is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time t_oh is 1.8 ns for PC133 components with no termination and 0 pF load.
6) If t_T is longer than 1 ns, a time (t_T - 1) ns has to be added to this parameter.
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-
Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times t_CK greater
or equal the specified t_WR value, where t_ck is equal to the actual system clock time.
9) When a Write command with Auto Precharge has been issued, a time of t_DAL(min) has be fullfilled before the next Activate Command can
be applied. For each of the terms, if not already an integer, round up to the next highest integer. t_CK is equal to the actual system clock time.
Rev. 1.1, 2007-02
14
09072006-N4GC-EREN