HYB39SC128800FE Datasheet, PDF (3/20 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Internet Data Sheet
1
Overview
HY[B/I]39SC128[800/160]FE
128-MBit Synchronous DRAM
This chapter lists all main features of the product family HY[B/I]39S128[800/160]FE and the ordering information.
1.1
Features
• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C Operating Temperature for HYB...
• -40 to 85 °C Operating Temperature for HYI...
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2 & 3
• Programmable Wrap Sequence: Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8 and full page
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (×8)
• Data Mask for Byte Control (×16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 4096 refresh cycles / 64 ms (15.6 µs)
• Random Column Address every CLK (1-N Rule)
• Single 3.3 V ± 0.3 V Power Supply
• LVTTL Interface
• Plastic Packages: PG–TSOPII–54 400 mil width
Product Type Speed Code
Speed Grade
Max. Clock Frequency
@CL3
@CL2
–6
PC166–333
f_CK3 166
t_CK3 6
t_AC3 5.4
t_CK2 7.5
t_AC2 5.4
–7
PC133–222
143
7
5.4
7.5
5.4
TABLE 1
Performance
Unit
—
MHz
ns
ns
ns
ns
1.2
Description
The HY[B/I]39S128[800/160]FE are four bank Synchronous
DRAM’s organized as 16 MBit ×8 and 8 Mbit ×16
respectively. These synchronous devices achieve high speed
data transfer rates for CAS latencies by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is
fabricated with Qimonda advanced 0.11 µm 128-MBit DRAM
process technology.
The device is designed to comply with all industry standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, data input and
output circuits are synchronized with the positive edge of an
externally supplied clock.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate than
is possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length, CAS latency
and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are
supported. These devices operate with a single 3.3 V ± 0.3 V
power supply. All 128-Mbit components are available in PG–
TSOPII–54 packages.
Rev. 1.1, 2007-02
3
09072006-N4GC-EREN