HYB18TC256160AF_1 Datasheet, PDF(7/55 Page) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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HYB18TC256160AF_1 Datasheet, PDF (7/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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Internet Data Sheet

HYB18TC256160AF

256-Mbit Double-Data-Rate-Two SDRAM

Ball#

Name

Ball

Type

Data Signals Ã16 organization

DQ0

I/O

DQ1

I/O

DQ2

I/O

DQ3

I/O

DQ4

I/O

DQ5

I/O

DQ6

I/O

DQ7

I/O

DQ8

I/O

DQ9

I/O

DQ10

I/O

DQ11

I/O

DQ12

I/O

DQ13

I/O

DQ14

I/O

DQ15

I/O

Data Strobe Ã16 organization

UDQS I/O

LDQS I/O

Data Mask Ã16 organization

UDM

LDM

Buffer

Type

SSTL

Power Supplies Ã16 organization

A9,C1,C3,C7, VDDQ

PWR â

A7,B2,B8,D2,

VDD

VSSQ

PWR â

A3,E3

VSS

PWR â

Power Supplies Ã16 organization

VREF

E9, G1, G3, G7, VDDQ

PWR â

E1, J9, M9, R1

E7, F2, F8, H2,

VDDL

VDD

VSSQ

PWR â

Function

Data Signal 15:0

Note: Bi-directional data bus. DQ[15:0]

Data Strobe Upper Byte

Note: UDQS corresponds to the data on DQ[15:8]

Data Strobe Lower Byte

Note: LDQS corresponds to the data on DQ[7:0]

Data Mask Upper/Lower Byte

Note: LDM and UDM are the input mask signals for Ã16 components and

control the lower or upper bytes.

I/O Driver Power Supply

Power Supply

I/O Driver Power Supply

Power Supply

I/O Reference Voltage

I/O Driver Power Supply

Power Supply

I/O Driver Power Supply

Rev. 1.20, 2007-04

03062006-H3V1-XJT4

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