HYB18TC256160AF_1 Datasheet, PDF (13/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
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Field
BA2
Bits Type¹⁾
16 reg. addr.
BA1
15
BA0
14
A13
13 w
Qoff
12 w
RDQS 11 w
DQS 10 w
OCD [9:7] w
Program
AL
[5:3] w
Description
TABLE 10
Extended Mode Register Definition (BA[2:0] = 001_B)
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
1_B BA0 Bank Address
Address Bus [13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0_B A13 Address bit 13
Output Disable
0_B QOff Output buffers enabled
1_B QOff Output buffers disabled
Read Data Strobe Output (RDQS, RDQS)
0_B RDQS Disable
1_B RDQS Enable
Complement Data Strobe (DQS Output)
0_B DQS Enable
1_B DQS Disable
Off-Chip Driver Calibration Program
000_B OCD OCD calibration mode exit, maintain setting
001_B OCD Drive (1)
010_B OCD Drive (0)
100_B OCD Adjust mode
111_B OCD OCD calibration default
Additive Latency
Note: All other bit combinations are illegal.
000_B AL 0
001_B AL 1
010_B AL 2
011_B AL 3
100_B AL 4
Rev. 1.20, 2007-04
13
03062006-H3V1-XJT4