HYB18TC256160AF_1 Datasheet, PDF (25/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
Symbol
Description
Min.
Nominal Max.
Unit
Notes
—
Output Impedance step size
for OCD calibration
0
—
1.5
Ω
4)
S_OUT
Output Slew Rate
1.5
—
5.0
V / ns
1)5)6)7)8)
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: V_DDQ = 1.7 V, V_OUT = 1420 mV; (V_OUT–V_DDQ) / I_OH must be less than 23.4
ohms for values of V_OUT between V_DDQ and V_DDQ – 280 mV. Impedance measurement condition for output sink dc current: V_DDQ = 1.7 V;
V_OUT = –280 mV; V_OUT / I_OL must be less than 23.4 Ohms for values of V_OUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) Slew Rates according to Chapter 8.2 V_IL(ac) to V_IH(ac) with the load specified in Figure 71.
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQ and t_QHS
specification.
8) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.20, 2007-04
25
03062006-H3V1-XJT4