HYB18TC256160AF_1 Datasheet, PDF(6/55 Page) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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HYB18TC256160AF_1 Datasheet, PDF (6/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

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Internet Data Sheet

HYB18TC256160AF

256-Mbit Double-Data-Rate-Two SDRAM

Configuration

The chip configuration of a DDR2 SDRAM is listed by function in Table 5. The abbreviations used in the Ball# and Buffer Type

columns are explained in Table 6 and Table 7 respectively. The ball numbering for the FBGA package is depicted in Figure 1.

Ball#

Name

Ball

Type

Clock Signals Ã16 organization

CKE

Control Signals Ã16 organization

RAS

CAS

Address Signals Ã16 organization

BA0

BA1

A10

A11

A12

Buffer

Type

SSTL

Function

TABLE 5

Chip Configuration

Clock Signal CK, Complementary Clock Signal CK

Clock Enable

Row Address Strobe (RAS), Column Address Strobe (CAS), Write

Enable (WE)

Chip Select

Bank Address Bus 1:0

Address Signal 12:0, Address Signal 10/Autoprecharge

Rev. 1.20, 2007-04

03062006-H3V1-XJT4

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