HYB18TC256160AF_1 Datasheet, PDF (15/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
%$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $




65)

'&&
3$65
UHJDGGU
03%7
Field Bits
Type¹⁾
TABLE 11
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010_B)
Description
BA2 16
w
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
BA [15:14] w
A
[13:7] w
0_B BA2 Bank Address
Bank Adress[15:14]
00_B BA MRS
01_B BA EMRS(1)
10_B BA EMRS(2)
11_B BA EMRS(3): Reserved
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0_B A[13:0] Address bits
A
7
w
Address Bus[7], adapted self refresh rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
A
[6:4] w
Address Bus[6:4]
0_B A[6:4] Address bits
A
3
w
Address Bus[3], Duty Cycle Correction (DCC)
0_B A[3] DCC disabled
1_B A[3] DCC enabled
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case £ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
Rev. 1.20, 2007-04
15
03062006-H3V1-XJT4