HYB18TC256160AF_1 Datasheet, PDF (17/55 Pages) Qimonda AG – 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM

Internet Data Sheet
HYB18TC256160AF
256-Mbit Double-Data-Rate-Two SDRAM
ODT Truth Tables
The ODT Truth Table shows which of the input pins are
terminated depending on the state of address bit A10 and
A11 in the EMRS(1). To activate termination of any of these
pins, the ODT function has to be enabled in the EMRS(1) by
address bits A6 and A2.
Input Pin
×16 Components
DQ[7:0]
DQ[15:8]
LDQS
LDQS
UDQS
UDQS
LDM
UDM
EMRS(1) Address Bit A10
X
X
X
0
X
0
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
TABLE 13
ODT Truth Table
EMRS(1) Address Bit A11
X
X
Rev. 1.20, 2007-04
17
03062006-H3V1-XJT4