HYB18T512161B2F Datasheet, PDF (7/37 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Ball#
Name
B3
UDM
F3
LDM
Power Supplies
A9,C1,C3,C7,C9
A1
A7,B2,B8,D2,D8
A3,E3
Power Supplies
V_DDQ
V_DD
V_SSQ
V_SS
J2
E9, G1, G3, G7, G9
J1
E1, J9, M9, R1
E7, F2, F8, H2, H8
J7
A3, E3,J3,N1,P9
Not Connected
V_REF
V_DDQ
V_DDL
V_DD
V_SSQ
V_SSDL
V_SS
A2, E2, R3, R7, R8, L1 NC
Other Balls
K9
ODT
Ball
Type
I
I
Buffer
Type
SSTL
SSTL
PWR –
PWR –
PWR –
PWR –
AI
–
PWR –
PWR –
PWR –
PWR –
PWR –
PWR –
NC
–
I
SSTL
Function
Data Mask Upper/Lower Byte
Note: LDM and UDM are the input mask signals and control the
lower or upper bytes.
I/O Driver Power Supply
Power Supply
I/O Driver Power Supply
Power Supply
I/O Reference Voltage
I/O Driver Power Supply
Power Supply
Power Supply
I/O Driver Power Supply
Power Supply
Power Supply
Not Connected
On-Die Termination Control
Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS,
UDM and LDM signal. An EMRS(1) control bit enables or
disables the ODT functionality.
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 3
Abbreviations for Ball Type
Rev. 1.1, 2007-06
7
05152007-ZYAH-ACMZ