HYB18T512161B2F Datasheet, PDF (14/37 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Input Pin
LDM
UDM
EMRS(1) Address Bit A10
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
EMRS(1) Address Bit A11
Burst Length
4
8
Starting Address
(A2 A1 A0)
x00
x01
x10
x11
000
001
010
011
100
101
110
111
Sequential Addressing
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
TABLE 11
Burst Length and Sequence
Interleave Addressing
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Notes
1. PageSize and Length is a function of I/O
organization:32Mb (CA[9:0]); Page Size = 2 kByte; Page
Length = 1024
2. Order of burst access for sequential addressing is “nibble-
based” and therefore different from SDR or DDR
components
Rev. 1.1, 2007-06
14
05152007-ZYAH-ACMZ