HYB18T512161B2F Datasheet, PDF (13/37 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Field Bits
Type¹⁾
Description
Partial Self Refresh for 4 banks
PASR [2:0] w
Address Bus, Partial Array Self Refresh for 4 Banks³⁾
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[1:0]=00, 01)
010_B PASR2 Quarter Array (BA[1:0]=00)
011_B PASR3 Not defined
100_B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5 Half array (BA[1:0]=10, 11)
110_B PASR6 Quarter array (BA[1:0]=11)
111_B PASR7 Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
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UHJD GGU
03 % 7
Field
BA1
Bits
14
Type¹⁾
BA0
13
A
[12:0] w
1) w = write only
TABLE 9
EMR(3) Programming Extended Mode Register Definition (BA[1:0]=10_B)
Description
Bank Adress[1]
1_B BA1 Bank Address
Bank Adress[0]
1_B BA0 Bank Address
Address Bus[12:0]
0_B A[12:0] Address bits
Input Pin
DQ[7:0]
DQ[15:8]
LDQS
LDQS
UDQS
UDQS
EMRS(1) Address Bit A10
X
X
X
0
X
0
TABLE 10
ODT Truth Table
EMRS(1) Address Bit A11
X
X
Rev. 1.1, 2007-06
13
05152007-ZYAH-ACMZ