HYB18T512161B2F Datasheet, PDF (26/37 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
Parameter
Symbol –20
Min.
Max.
TABLE 29
Timing Parameter by Speed Grade
–25
Min.
Max.
Unit Notes¹⁾
2)3)4)5)6)
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge
t_DAL
time
–450
2
0.45
3
0.45
WR + t_RP
+450
—
0.55
—
0.55
—
–500
2
0.45
3
0.45
WR + t_RP
+500
—
0.55
—
0.55
—
ps
t_CK
t_CK
t_CK
t_CK
t_CK
7)18)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_DELAY
t_IS + t_CK + t_IH ––
t_IS + t_CK + t_IH ––
ns ⁸⁾
DQ and DM input hold time (differential data t_DH
145
strobe)
––
250
––
ps ⁹⁾
DQ and DM input hold time (single ended data t_DH1
strobe)
-105
––
0
––
ps ⁹⁾
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
0.35
–450
0.35
—
—
+450
—
280
0.35
–500
0.35
—
—
+500
—
280
t_CK
ps ⁹⁾
t_CK
ps ¹⁰⁾
Write command to 1st DQS latching transition t_DQSS
DQ and DM input setup time (differential data t_DS
strobe)
WL – 0.25
20
WL +
0.25
WL – 0.25
125
WL + t_CK
0.25
––
ps ⁹⁾
DQ and DM input setup time (single ended data t_DS1
strobe)
-105
0
––
ps ⁹⁾
DQS falling edge hold time from CK (write cycle) t_DSH
DQS falling edge to CK setup time (write cycle) t_DSS
Clock half period
t_HP
Data-out high-impedance time from CK / CK t_HZ
Address and control input hold time
t_IH
Address and control input pulse width
t_IPW
(each input)
0.2
—
0.2
—
t_CK
0.2
—
0.2
—
t_CK
MIN. (t_CL, t_CH) —
MIN. (t_CL, t_CH) —
11)
—
t_AC.MAX —
t_AC.MAX ps
12)
525
575
—
ps
0.6
—
0.6
—
t_CK
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
t_IS
t_LZ(DQ)
t_LZ(DQS)
t_MRD
400
2×
t_AC.MIN
t_AC.MIN
2
t_AC.MAX
t_AC.MAX
—
450
2×
t_AC.MIN
t_AC.MIN
2
—
ps
t_AC.MAX ps
12)
t_AC.MAX ps
12)
—
t_CK
Rev. 1.1, 2007-06
26
05152007-ZYAH-ACMZ