HYB18T512161B2F Datasheet, PDF (12/37 Pages) Qimonda AG – 512-Mbit x16 DDR2 SDRAM

Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
Field
AL
Bits
[5:3]
Type¹⁾
R_TT
6,2
DIC
1
DLL
0
1) w = write only register bits
Description
Additive Latency
Note: All other bit combinations are illegal.
000_B AL 0
001_B AL 1
010_B AL 2
011_B AL 3
100_B AL 4
101_B AL 5
110_B AL 6
Nominal Termination Resistance of ODT
00_B RTT ∞ (ODT disabled)
01_B RTT 75 Ohm
10_B RTT 150 Ohm
11_B RTT 50 Ohm
Off-chip Driver Impedance Control
0_B DIC Full (Driver Size = 100%)
1_B DIC Reduced
DLL Enable
0_B DLL Enable
1_B DLL Disable
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UHJDGGU
Field Bits
BA1 14
BA0 13
A
[12:8]
SRF 7
A
[6:3]
Type¹⁾
TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[1:0]=10_B)
Description
reg. addr.,
w
w
w
Bank Address [1]
1_B BA1 Bank Address
Bank Address [0]
0_B BA0 Bank Address
Address Bus
00000_B A Address bits
Address Bus, High Temperature Self Refresh Rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
Address Bus
0000_B A Address bits
Rev. 1.1, 2007-06
12
05152007-ZYAH-ACMZ