HYS64T128020EML-3S-B Datasheet, PDF (6/39 Pages) Qimonda AG – 214-Pin Unbuffered DDR2 SDRAM MicroDIMM Modules Low Power

Preliminary Internet Data Sheet
HYS64T128020EML-[3S/3.7/5]-B
Unbuffered DDR2 SDRAM MicroDIMM Modules
Ball No.
Name
46
BA2
NC
161
A0
159
A1
52
A2
158
A3
51
A4
50
A5
157
A6
48
A7
155
A8
154
A9
54
A10
AP
47
A11
153
A12
167
A13
NC
Data Signals
3
4
9
10
109
110
114
115
12
13
21
22
117
118
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
Pin
Type
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
Buffer
Type
SSTL
–
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
Function
Bank Address Bus 2
Note: Greater than 512Mb DDR2 SDRAMS
Not Connected
Note: Less than 1Gb DDR2 SDRAMS
Address Inputs 12:0, Address Input 10/Autoprecharge
Note: During a Bank Activate command cycle, defines the row address
when sampled at the crosspoint of the rising edge of CK and falling
edge of CK. During a Read or Write command cycle, defines the
column address when sampled at the cross point of the rising edge
of CK and falling edge of CK. In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is HIGH, autoprecharge is selected and
BA[2:0] defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP
is used in conjunction with BA[2:0] to control which bank(s) to
precharge. If AP is HIGH, all banks will be precharged regardless
of the state of BA[2:0] inputs. If AP is LOW, then BA[2:0] are used
to define which bank to precharge.
Address Input 13
Note: Modules based on ×4/×8 component
Not Connected
Note: Modules based on ×16 component
I/O
SSTL
Data Bus 0:38
I/O
SSTL
Note: Data Input/Output pins
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
I/O
SSTL
Rev. 0.5, 2007-05
6
05212007-7F24-MITO